View HFA3842_214278.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HFA3842
TM
P RE L I M I NA R Y
Data Sheet
June 2000
File Number
4839
Wireless LAN Medium Access Controller
The Intersil HFA3842 Wireless LAN Medium Access Controller is part of the PRISM(R) 2.4GHz radio chip set. The HFA3842 directly interfaces with the Intersil HFA386x family of Baseband Processors, offering a complete end-to-end chip set solution for wireless LAN products. Protocol and PHY support are implemented in firmware to allow custom protocol and different PHY transceivers. The HFA3842 is designed to provide maximum performance with minimum power consumption. Package pin layout provides optimal PC board layout to all user interfaces including PCMCIA and USB. Firmware implements the full IEEE 802.11 Wireless LAN MAC protocol. It supports BSS and IBSS operation under DCF, and operation under the optional Point Coordination Function (PCF). Low level protocol functions such as RTS/CTS generation and acknowledgement, fragmentation and de-fragmentation, and automatic beacon monitoring are handed without host intervention. Active scanning is performed autonomously once initiated by host command. Host interface command and status handshakes allow concurrent operations from multi-threaded I/O drivers. Additional firmware functions specific to access point applications are also available. Designing wireless protocol systems using the HFA3842 is made easier with the availability of evaluation board, firmware, software device drivers, and complete documentation. The HFA3842 is a WLAN MAC Controller IC, based on the HFA3841. Pin-for-pin upgrade replacement for the HFA3841.
Features
* IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps * Part of the Intersil PRISM Wireless LAN Chip Set * Full Implementation of the MAC Protocol Specified in IEEE Standards 802.11-1999 and 802.11b * PCMCIA Host Interface Supports Full 16-Bit Implementation of PC Card 16 (1995), also ISA PnP with Additional Chip * Host Interface Provides Dual Buffer Access Paths * External Memory Interface Supports up to 4M bytes RAM * Internal Encryption Engine Executes IEEE802.11 WEP * Low Power Operation; 25mA Active, 8mA Doze, <1mA Sleep * Operation at 2.7V to 3.6V Supply * 3V to 5V Tolerant Input/Outputs * 128 Pin LQFP Package Targeted for Type II PC Cards * IEEE802.11 Wireless LAN MAC Protocol Firmware and Microsoft(R) Windows(R) Software Drivers * Pin for Pin Replacement for the HFA3841 Supporting all Functions and operations of the HFA3841
Applications
* High Data Rate Wireless LAN * PC Card Wireless LAN Adapters * USB Wireless LAN Adapters * PCI Wireless LAN Cards (Using Ext. Bridge Chip) * Wireless LAN Modules * Wireless LAN Access Points * Wireless Bridge Products * Wireless Point-to-Multipoint Systems * ISA, ISA PnP WLAN Cards
New Features of the HFA3842
* USB Host Interface supports USB V1.1 at 12Mbps, and is an alternative to the PC Card host interface. * New start up modes allow the PCMCIA Card Information Structure to be initialized from a serial EEPROM. This allows firmware to be downloaded from the host, eliminating the parallel Flash memory device. * Firmware can be loaded from serial Flash memory. * Direct attachment to a typical x16 SRAM using five control signals (RAMCS_, MOE_, MWEL_, MLBE_, and MUBE_). * Low frequency crystal oscillator to maintain time and allow baseband clock source to power off during sleep mode. * Improved performance of internal WEP engine. * On-chip execution can now be viewed while in degug mode. * Independent programmable cycle of timing for external chip selects allows attachment of slow memory devices without compromising higher speed instruction execution. * Pinout is backward compatible with HFA3841. 2-1
Ordering Information
PART NUMBER HFA3842IN HFA3842IN96 HFA3842IK HFA3842IK96 TEMP. RANGE (oC) -45 to 85 -45 to 85 -40 to 85 -40 to 85 PACKAGE 128 Ld LQFP Tape and Reel BGA 12x12 Tape and Reel V160.12x12A PKG. NO. Q128.14x20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. Microsoft(R) and Windows(R) are registered trademarks of Microsoft Corporation.
HFA3842 Pinout
128 LEAD LQFP
HD8 HD9 HD10 PL7 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 VCC_IO3 VSS_IO3 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0/MWEHHREGHD0 HD1 HD2 VCC_IO3 VSS_IO3 NVCSVSS_IO3 VCC_IO3 MWELMOERAMCS-
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PJ4
HCE1HD7 HD6 HD5 HD4 HD3 PJ6 PJ5 PJ7 TCLKIN USBUSB+ VSS_CORE3 VCC_CORE3 PL0 RESET TXD TXC RXD RXC PK5 PK6 PK7 VSS_CORE3 VCC_CORE3 PL2 PL1 PL3 PJ3 PJ1 PJ0 PJ2 PK2 PK1 PK0 HSTSCHGVSS_CORE3
Simplified Block Diagram
PRISM RADIO BASEBAND PROCESSOR TXD/RXD CTRL/STATUS SERIAL CONTROL HFA3842 MICROPROGRAMMED MAC ENGINE PC CARD HOST INTERFACE WEP ENGINE USB HOST INTERFACE MEMORY CONTROLLER ON-CHIP ROM ON-CHIP RAM HOST COMPUTER DATA ADDRESS CONTROL
PHY INTERFACE (MDI)
PRISM RADIO RF SECTION
SERIAL CONTROL (MMI)
USB
RADIO AND SYNTH SERIAL CONTROL
ADDRESS
44MHz CLOCK SOURCE
THE 3842 MUST BE SUPPLIED WITH A
SEPARATE 48MHz CLOCK WHEN USB IS USED.
EXTERNAL SRAM AND FLASH MEMORY
DATA
2-2
SELECT
CLKOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
HINPACKHWAITSB ATTACHED HA0 HA1 HA2 HA3 HA4 HA5 HA6 HA7 HIREQVSS _IO3 HWEHA8 HA9 HIOWRHIORDHOEHCE2HD15 VCC _IO3 HD14 HD13 HD12 HD11
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
INDEX
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
PK4 PK3 MLBEMD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 VCC_CORE3 VSS_IO3 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 PL4 VSS_IO3 LFXTALO CLKIN LFXTALI
HFA3842 HFA3842 Pin Descriptions
HOST INTERFACE PINS PIN NAME HA0-9 HCE1HCE2HD0-15 PIN NUMBER PIN I/O TYPE DESCRIPTION PC Card Address Input, Bits 0 to 9 PC Card Select, Low Byte PC Card Select, High Byte PC Card Data Bus, Bit 0 to 15
106-113, 117, 118 5V tol, CMOS, Input, 50K Pull Down 1 122 101-99, 6-2, 96-94, 128-125, 123 103 120 119 114 121 102 16 36 104 116 12 11 105 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up 5V tol, BiDir, 2mA, 50K Pull Down
HINPACKHIORDHIOWRHRDY/HIREQHOEHREGHRESET HSTSCHGHWAITHWEUSB+ USBUSB ATTACHED
CMOS Output, 2mA 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up CMOS Output, 4mA 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, Input, 50K Pull Up 5V tol, CMOS, ST Input, 50K Pull Up CMOS Output, 4mA CMOS Output, 4mA 5V tol, CMOS Input, 50K Pull Up CMOS BiDir, 2mA, (Also USB Transceiver) CMOS BiDir, 2mA, (Also USB Transceiver) Input, 5V Tolerant, Pull-Down TABLE 1. MEMORY INTERFACE PINS
PC Card I/O Decode Confirmation PC Card I/O Space Read PC Card I/O Space Write PC Card interrupt Request (I/O Mode) Card Ready (Memory Mode) PC Card Memory Attribute Space Output Enable PC Card Attribute Space Select Hardware Reset PC Card Status Change PC Card Not Ready (Force Host Wait State) PC Card Memory Attribute Space Write Enable USB, MBUS Address Bit 20, or I/O as PL5 USB, MBUS Address Bit 21, or I/O or I/O as PL6 Sense USB VBUS to Indicate Cable Attachment
PIN NAME MUBE- / MA0 / MWEHMA1-18 PL4 PL5 PL6 MLBEMOEMWE- / MWELRAMCSNVCSMD0-7 MD8-15 NOTE:
PIN NUMBER 72
PIN I/O TYPE CMOS TS Output, 2mA
DESCRIPTION MBUS Upper Byte Enable for x16 Memory; MBUS Address Bit 0 (byte) for x8 Memory; High Byte Write Enable for 2 x8 Memories MBUS Address Bits 1 to 18 MBUS Address Bit 19 MBUS Address Bit 20 (See Note 1) MBUS Address Bit 21 (See Note 1) MBUS Lower Byte Enable, or I/O as PM2 Memory Output Enable Low (or only) Byte Memory Write Enable RAM Select NV Memory Select MBUS Low Data Byte, Bits 0 to 7 MBUS High Data Byte, Bits 8 to 15
73-81, 84-92 43 12 11 62 70 71 69 68 61-54 51-44
CMOS TS Output, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA CMOS TS Output, 2mA, 50K Pull Up CMOS TS Output, 2mA CMOS TS Output, 2mA CMOS TS Output, 2mA CMOS TS Output, 2mA 5V tol, CMOS, BiDir, 2mA, 100K Pull Up 5V tol, CMOS, BiDir, 2mA 50K Pull Down
1. Not available if USB interface is used. TABLE 2. RADIO INTERFACE AND GENERAL PURPOSE PORT PINS PIN NAME TXD TXC RXD RXC PIN NUMBER 17 18 19 20 PIN I/O TYPE CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA CMOS Input CMOS Input DESCRIPTION OF FUNCTION (IF OTHER THAN IO PORT) Transmit Data Out Transmit Clock In/Out Receive Data In Receive Clock In
2-3
HFA3842
TABLE 2. RADIO INTERFACE AND GENERAL PURPOSE PORT PINS (Continued) PIN NAME PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0 PL1 PL2 PL3 PL4 PL5 (USB+) PL6 (USB-) PL7 PIN NUMBER 31 30 32 29 65 8 7 9 35 34 33 63 64 21 22 23 15 27 26 28 43 12 11 93 PIN I/O TYPE CMOS BiDir, 2mA, ST, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA CMOS BiDir, 2mA, 50K Pull Up CMOS BiDir, 2mA, ST, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA, 50K Pull Down CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA CMOS BiDir, 2mA, (Also USB Transceiver) CMOS BiDir, 2mA, (Also USB Transceiver) CMOS BiDir, 2mA, Pull Down TABLE 3. CLOCKS PIN NAME CLKIN LFXTALI LFXTALO CLKOUT TCLKIN PIN NUMBER 40 39 41 38 10 PIN I/O TYPE CMOS Input, ST Pull Down Analog Input CMOS Output, 2mA CMOS, TS Output, 2mA CMOS BiDir, 2mA, 50K Pull Down TABLE 4. POWER PIN NAME VCC_CORE3 VCC_IO3 VCC_IO5 VSS_CORE3 VSS_IO3 PIN NUMBER 14, 25, 53 66, 83, 98, 124 105 13, 24, 37 42, 52, 67, 82, 97, 115 PIN I/O TYPE 3.3V Core Supply 3.3V I/O Supply 5V Tolerance Supply Core VSS I/O VSS DESCRIPTION DESCRIPTION External Clock Input (at >= 2X Desired MCLK Frequency, Typically 44-48MHz) 32.768kHz Crystal Input (Note 2) 32.768kHz Crystal Output Clock Output (Selectable as MCLK, TCLK, or TOUT0) Alternate clock input for timers DESCRIPTION OF FUNCTION (IF OTHER THAN IO PORT) MMI Clock (SCLK) MMI Serial Data Out (SDO) MMI Serial Data In (SDI) MMI Device Enable 0 (SDE0) MMI Device Enable 1 (SDE1) MBUS Request (MREQ-) MBUS Grant (MGNT-); LED #2 LED #1 MPSI Clock MPSI Data Out MPSI Data In MPSI Device Select 0 MPSI Device Select 1 PHY Data Available (PDA), or I/O PHY Medium Busy (MBUSY), or I/O PHY Energy Detect (EDET), or I/O Transmitter Enable (TXE), or I/O Receiver Enable (or PHY Sleep Control) PHY Reset (PHYRES)DA), or I/O Antenna Select (ANTSEL), or I/O MBUS Address Bit 19, or I/O USB, MBUS Address Bit 20, or I/O USB, MBUS Address Bit 21, or I/O PHY Transmit Ready (TXR), or I/O
ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with "-" are active low. NOTES: 2. Pin 39 (VCC_CORE3 in 3841), has been reassigned as LFXTALI. For 3841 compatibility, it may be tied to VCC. Pin 62 (TRST- in 3841) has been reassigned as MLBE. For 3841 compatibility, it may be tied low through 1K. Pin 105 (VCC_IO5 in 3841) has been reassigned as USB ATTACHED. For 3841 compatibility, it may be tied to VCC. Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at rated loads.
2-4
HFA3842
TABLE 5. PORT PIN USES FOR PRISM APPLICATION PIN 20 19 18 17 31 30 32 NAME RXC RXD TXC TXD PJ0 PJ1 PJ2 PRISM I USE RXC - Receive Clock RXD - Receive Data TXC - Transmit Clock TXD - Transmit Data SCLK - Clock for the SD Serial Bus SD - Serial Bidirectional Data Bus R/W - An input to the HFA3860A Used to Change the Direction of the SD Bus When Reading or Writing Data on the SD Bus CS - A Chip Select for the Device to Activate the Serial Control Port (Active Low) Not Used PRISM II USE RXC - Receive Clock RXD - Receive Data TXC - Transmit Clock TXD - Transmit Data SCLK - Clock for the SD Serial Bus SD - Serial Bi-Directional Data Bus Not Used
29 65 8
PJ3 PJ4 PJ5
CS_BAR - Chip Select for HFA3861 Baseband (Active Low) PE1 - Power Enable 1
SYNTH_LE - Latches a Frame of 22 Bits After it has LE_IF - Load Enable for HFA3783 Quad IF Been Shifted by the SCLK into the Synthesizer Registers LED - Activity Indicator Not Used Not Used Not Used Not Used TX_PE_RF - Power Enable RX_PE_RF - Power Enable MD_RDY - Header Data and Data Packet are Ready to be Transferred From Baseband on RXD LED - Activity Indicator RADIO_PE - RF Power Enable LE_RF - Load Enable for HFA3983 RF Chip SYNTHCLK - Serial Clock to Front End Chips SYNTHDATA - Serial Data to Front End Chips PA_PE - Transmit PA Power Enable PE2 - Power Enable 2 MDREADY - Header Data and Data Packet are Ready to be Transferred from Baseband on RXD
7 9 35 34 33 63 64 21 22 23 15 27 26 28 43 12 11 93
PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7
CCA - Signal that the Channel is Clear to Transmit CCA - Signal that the Channel is Clear to Transmit RADIO_PE - Master Power Control for the RF Section CAL_EN - Calibration Mode Enable
TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband RX_PE - Receive Enable to Baseband RESET - Reset to Baseband Not Used MA19 (If Required) MA20 (If Required) MA21 (If Required) TX_RDY - Baseband Ready to Receive Data on TXD (Not Used By Firmware) RX_PE - Receive Enable to Baseband RESET_BB - Reset Baseband T/R-SW_BAR - Transient/Receive Control (Inverted) MA19 (If Required) MA20 (If Required) or USB+ MA21 (If Required) or USBT/R_SW - Transmit/Receive Control
2-5
HFA3842
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) LQFP Package . . . . . . . . . . . . . . . . . . . 56 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .100oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.70V to +3.60V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical One Input Voltage Logical Zero Input Voltage Logical One Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance
Maximum Test Temperature = 100oC, VCC = 3.0V to 3.3V 10% TA = -40oC to 85oC SYMBOL ICCOP ICCSB II IO VIH VIL VOH VOL CIN COUT TEST CONDITIONS VCC = 3.6V, CLK Frequency 44MHz VCC = Max, Outputs not Loaded VCC = Max, Input = 0V or VCC VCC = Max, Input = 0V or VCC VCC = Max, Min VCC = Min, Max IOH = -1mA, VCC = Min IOL = 2mA, VCC = Min CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC CLK Frequency 1MHz. All measurements referenced to GND. TA = 25oC MIN -10 -10 0.7VCC VCC-0.2 TYP 35 0.5 1 1 0.2 5 5 MAX 45 1 10 10 VCC/3 0.2 10 10 UNITS mA mA uA uA V V V V pF pF
4. All values in this table have not been measured and are only estimates of the performance at this time.
AC Electrical Specifications
PARAMETER CLOCK SIGNAL TIMING OSC Clock Period (Typ. 44MHz) High Width Low Width Delay from OSC Edge to MCLK Edge EXTERNAL MEMORY INTERFACE Rising Edge MCLK to MA[15:0], RAMCSx- MOE-, MWExWidth MOEMD[15:0] Read Data Setup to MCLK Rising Edge MD[15:0] Read Data Hold after MOE- Rising Edge Minimum Width between Read and Write Width MWExMWEX- Rising to RAMCS Rising MD[15:0] Write Data Hold Time to Rising Edge MWExtD1 tD2 tS1 tH1 tD3 tD4 tD5 tD6 0 24 0 0 tMCLK tMCLK / 4 tMCLK /2 tMCLK / 4 10 3/4 ns ns ns ns ns ns ns ns tCYC tH1 tL1 tD1 22 15 15 22.7 11.36 11.36 10 200 ns ns ns ns SYMBOL MIN TYP MAX UNITS
2-6
HFA3842
AC Electrical Specifications
SYNTHESIZER SYNTHCLK (PK1) Period SYNTHCLK (PK1) Width Hi SYNTHCLK (PK1) Width Lo SYNTHDATA (PK2) Hold Time from Falling Edge of SYNTHCLK (PK1) SYNTHCLK (PK1) Falling Edge to SYNLE Inactive SERIAL PORT - HFA3824A/HFA3860B SYNTHCLK (PK1) Clock Period High Period Delay from Clock Falling Edge to SPCSx, SPAS, SPREAD, SYNTHDATA (PK2) Outputs Setup Time of SYNTHDATA (PK2) Read to SYNTHCLK (PK1) Falling Edge Hold Time of SYNTHDATA (PK2) Read from SYNTHCLK (PK1) Falling Edge Hold Time of SYNTHDATA (PK2) Write from SYNTHCLK (PK1) Falling Edge SYSTEM INTERFACE - PC CARD IO READ 16 Data Delay After HIORDData Hold Following HIORDHIORD- Width Time Address Setup Before HIORDAddress Hold Following HIORDHCE(1, 2)- Setup Before HIORDHCE(1, 2)- Hold After HIORDHREG- Setup Before HIORDHREG- Hold Following HIORDHINPACK- Delay Falling from HIORDHINPACK- Delay Rising from HIORDData Delay from HWAIT- Rising HWAIT- Width Time SYSTEM INTERFACE - PC CARD IO WRITE 16 Data Setup Before HIORDData Hold Following HIORDHIOWR- Width Time Address Setup Before HIORDAddress Hold Following HIORDHCE(1, 2)- Setup Before HIORDHCE(1, 2)- Hold Following HIORDHREG- Setup Before HIORDHREG- Hold Following HIORDHWAIT- Delay Falling from HIORDHWAIT- Width Time HIOWR- High from HWAIT- High tSUIOWR tHIOWR tWIOWR tSUA tHA tSUCE tHCE tSUREG tHREG tDFWT tWWT tDRIOWR 60 30 165 70 20 5 20 5 0 0 35 12,000 ns ns ns ns ns ns ns ns ns ns ns ns tDIORD tHIORD tWIORD tSUA tHA tSUCE tHCE tSUREG tHREG tDFINPACK dDRINPACK tDRWT tWWT 0 165 70 20 5 20 5 0 0 100 45 45 0 12,000 ns ns ns ns ns ns ns ns ns ns ns ns ns tCYC tH1, tL1 tCD tDRS tDRH tDWH 90ns tCYC/2 -10 15 0 0 10 4s tCYC/2 + 10 ns ns tCYC tH1 tL1 tD2 tD3 90 tCYC /2 - 10 tCYC /2 - 10 0 35 4,000 tCYC /2 + 10 tCYC /2 + 10 ns ns ns ns ns (Continued) SYMBOL MIN TYP MAX UNITS
PARAMETER
2-7
HFA3842
AC Electrical Specifications
RADIO TX DATA - TX PATH TXC Rising to TXD TXC Period TXC Width Hi TXC Width Lo MCLK Period TXC Rising to TX_PE2 Deassert (See Note 12) TX_RDY Assert Before TXC Rising TX_RDY Hold After TXC Rising (See Note 5) RADIO RX DATA - RX PATH RX_RDY Setup Time to RXC Positive Edge (See Note 6) RX_RDY Hold Time from RXC Positive Edge (See Note 7) RX_PE2 Delay from RX_RDY deAssert (See Note 11) RX_PE2 Low Pulse Width (See Note 10) RXD Setup Time to RXC Positive Edge (See Note 8) RXD Hold Time from RXC Positive Edge (See Note 8) RXC Period (See Note 12) MCLK Period RXC Width Hi RXC Width Lo NOTES: 5. TX_RDY is and'd with TXC_ONE_SHOT to shift data in shift register. However, once the last data bit is put on TXD output pin no further shifting of bits is required. In addition, TX_RDY remains asserted until TX_PE2 is de-asserted which occurs several MAC MCLK's after the last data bit is shifted into the BBP TX_PORT. Therefore, 0ns hold time is required for this signal. TX_RDY is used by the BBP to signal that the PLCP header and preamble have been generated and the MAC must provide the MPDU data. TX_RDY will remain asserted until TX_PE2 is deasserted by the MAC. TX_PE2 is async to the TX_PORT. 6. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time. 7. MD_RDY is and'd with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held active until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY (MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP header length field are received. Therefore, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY signal be cleared when the last RXD bit is received the hold time w/r RXC must be honored. 8. RXC positive edge clocks a flop which stores the RXD for internal usage. 9. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low. Since RXC can be async to MAC MCLK it is assumed that 3 MCLK periods will suffice. 10. RX_PE inactive width at BBP is 3 BBP MCLK's. Since BBP MCLK and MAC MCLK can be async minimum should be 4 MAC MCLK's. 11. When RX_RDY drops before expected number of RXD bits is received, then TX/RX FSM in mpctl.v signals timers which clear rx_pe2_int. 12. Need to sample 1 RXC high and 1 RXC low with MAC MCLK. tSURX_RDY tHRX_RDY tDRX_PE2 tWRX_PE2 tSURXD tHRXD tRXC tMCLK tRCHM tRCLM 10 45 10 0 22.7 31 31 3 * tMCLK 4 * tMCLK 3 * tMCLK ns ns ns ns ns ns ns ns ns ns tDTXD tTXC tCHM tCLM ttMCK tDTX_PE2 tTX_RDY tTX_RDYH 4* tTMCK 31 31 22.7 10 0 TBD 10 TBD ns ns ns ns ns ns ns (Continued) SYMBOL MIN TYP MAX UNITS
PARAMETER
2-8
HFA3842
TABLE 6. SPECIAL HARDWARE FUNCTIONS FOR PORT PINS PJ0 PJ1 SCK SDO/SDIO MOSI PJ2 SDI/MISO SDDIR PJ3 SDE0 PCSPHYCSPJ4 SDE1 SDDQ SSPJ5 PJ6 MREQMGNTLED2 PJ7 PK0 LED1 GPCK UHSIn PK1 GPDO UTXD PK2 GPDI URXD PK3 GPDS0 UHSOut PK4 PK5 GPDS1 PDA UWDET PK6 MBUSY RATE0 PK7 EDET RATE1 PL0 PL1 TXE RXE PHYSLP PL2 PL3 PHYRES SLOT ANTSEL PL4 MA19 USBLED0 PL5 MA20 USB+ PL6 PL7 MA21 TXR MMI Serial Clock In or Out MMI Serial Data Out or I/O SPI Master Out/Slave In MMI Serial Data In MMI (SDIO) Data Direction MMI Serial Device Enable 0 SPI/MMI Transfer Qualifier PHY Chip Select (3-3.5MB) MMI Serial Device Enable 1 MMI Data Delivery Qualifier SPI Slave Select MBUS Request MBUS Grant LED 2 Driver LED 1 Driver GP Serial Port Clock In Or Out Async Handshake In GP Serial Port Data Output Async Transmit Data GP Serial Port Data Input Async Receive Data GP Device Select 0 Async Handshake Out GP Device Select 1 PHY (or MAC) Data Available Unique Word Detected Medium Busy Data Rate Select 0 Energy (or Modulation) Detect Data Rate Select 1 Transmitter Enable Receiver Enable PHY Sleep PHY Reset Slot Time Reference (In or Out) Antenna Select MBUS Address Bit 19 USB Bus Data LED 0 Driver MBUS Address Bit 20 USB Bus Data + MBUS Address Bit 21 Transmitter Ready (Directly from I/O Port) For 1M Byte SRAM For USB Host Interface (Directly from I/O Port) For 2M Byte SRAM For USB Host Interface For 4M Byte SRAM Can Drive "Awake" LED (Directly from I/O Port) (Directly from I/O Port) Qualifies RXD Input to MAC controller Output from MAC Controller CCA Status (PHY-Dependent Source) Indicates GP Port Async Rx Ready Indicates External Async Rx Ready (Directly from I/O port) (Directly from I/O port) MMI Serial Clock In or Out MMI Serial Data Out or I/O Also for MicroWire Or SPI Master In/Slave Out Low while SDIO is Driven as an Output Generally Selects PHY Controller Asserted by Hardware During Transfer For Memory-Mapped PHY Controllers For Serial EPROM, Synthesizer, Etc. Low for Data on SDIO, High for Address In Slave Mode SCK is Serial Clock Input
2-9
HFA3842 Waveforms
OSC tH1 tCYC tH1
FIGURE 1. CLOCK SIGNAL TIMING
44MHz 23ns OSC 10ns (NOTE 13) 11MHz 91ns MCLK (INTERNAL) QCLK (INTERNAL) 23ns MCLKOUT 11.5ns ADDRESS, RAMCS_ 17ns MOE_ 24ns MD0-15 READ DATA VALID DATA AT MDIN 13ns MWEH/L_ tH0 MD0-15, WRITE DATA 20ns MBUS READ CYCLE MBUS WRITE CYCLE VALID DATA 16ns tH0 17ns
NOTE: 13. Timing delays between OSC and internal clocks are shown for information purposes only. FIGURE 2. MBUS MEMORY TIMING - 11MHz MCLK
2-10
HFA3842 Waveforms (Continued)
44MHz 23ns OSC 10ns (NOTE 15) 14.67MHz 68.2ns MCLK (INTERNAL) QCLK (INTERNAL)
10ns (NOTE 14)
10ns (NOTE 14)
MCLKOUT 11.5ns ADDRESS, RAMCS_ 17ns MOE_ 24ns MD0-15 READ DATA VALID DATA AT MDIN tH0 17ns
13ns MWEH/L_
16ns
tH0 MD0-15 WRITE DATA 20ns MBUS READ CYCLE MBUS WRITE CYCLE VALID DATA
NOTES: 14. 14.67MHz requires an odd divisor in the prescaler. Note that both edges of OSC are used to create MCLK and QCLK, thus a deviation from 50% duty cycle in OSC will result in corresponding changes in MBUS timing. 15. Timing delays between OSC and internal clocks are shown for information purposes only. FIGURE 3. MBUS MEMORY TIMING - 14.67MHz MCLK
SYNTHCLK (PK1) tH1 SYNLE SPCSPWR tD1 SYNTHDATA (PK2) D[n] tL1 tCYC tD2 D[n -1] D[n -2] D[2] D[1] D[0] tD3
FIGURE 4. SYNTHESIZER
2-11
HFA3842 Waveforms (Continued)
SYNTHCLK (PK1) TH1 SPCSX tCYC tCD SPAS tCD TL1 tCD
tCD SPREAD (READ)
tCD
tDRS tDRH SYNTHDATA (PK2) (READ) A[7] tCD SPREAD (WRITE) tDWH SYNTHDATA (PK2) (WRITE) A[7] A[6] A[0] D[7] D[1] D[0] A[6] A[0] D[1] D[0]
tCD
FIGURE 5. SERIAL PORT - HFA3824A/HFA3860B
HA[15:0] tSUREG HREGISUCE HCE(1, 2)tWIORD tDIORD HIORDNtSUA HINPACKtDFINPACK tDRINPACK tHA tHCE tHREG
HWAITtDFWT HD[15:0] tWWT tDRWT tHIORD
FIGURE 6. PC CARD IO READ 16
2-12
HFA3842 Waveforms (Continued)
HA[15:0] tSUREG HREGtHCE tHREG
tSUCE HCE (1, 2) tSUA tWIOWR
tHA HIOWRtDRINPACK tDRIOWR HWAITtDFWT tSUIOWR tWWT tHIOWR
HD[15:0]
FIGURE 7. PC CARD IO WRITE 16
TXDATA
TXCLK tTX_RDY TX_RDY
TX_PE2
FIGURE 8. TX PATH
2-13
HFA3842 Waveforms (Continued)
RXDATA
RXCLK tSURX_RDY RX_RDY tDRX_PE2 RX_PE2 tWRX_PE2 tHRX_RDY
CCA tCCAF
FIGURE 9. RX PATH
RXDATA
A
B
C
tRCHM
tSURXD
tHRXD
RXCLK tRCLM tRXCLK A B tMCLK
RXD_INT
MCLK
RXCLK_INT
RXCLK_INT2
RXCLK_ONE _SHOT
FIGURE 10. EXPANDED RX TIMING
2-14
HFA3842 HFA3842 System Overview
I/O BUS HOST SYSTEM (I/O DRIVER) HOST INTERFACE HFA3842 WIRELESS MAC CONTROLLER MAC BRIDGE FOR ACCESS POINT
FOR STATION ADAPTER
PHY TRANSCEIVER
WIRELESS MEDIUM
LAN DISTRIBUTION SYSTEM
FIGURE 11. TYPICAL APPLICATION
HFA3842 MD0..15 MA1..17 NVCS_ MOE_ MD0..7
FLASH 128Kx8
MA0..16 CS_ OE_
SRAM 128Kx8 MD0..7 MA1..17 OE_ MWEL_ MA0/MWEH_ RAMCS_ WE_ CS_ SRAM 128Kx8 MD8..15 MA1..17 OE_ WE_ CS_
FIGURE 12. 8-BIT MEMORY INTERFACE
2-15
HFA3842
FLASH 128Kx16 ADDR(0..16) DATA(0..15) CEOEMA0/MWEHWE
HFA3842 MA1..17 MD0..15 NVCS-
SRAM 128Kx16 ADDR(0..16) DATA(0..15) UBMLBERAMCSMOEMWELLBCEOE WE
FIGURE 13. 16-BIT MEMORY INTERFACE
External Memory Interface
The HFA3842 provides separate external chip selects for code space and data storage space. Code space is accessible as data space through an overlay mechanism, except for an internal ROM. Refer to Figures 12 and 13 for HFA3842 memory configuration details. The maximum possible memory space size is 4Mbytes. If USB is the host interface, this is reduced to 1Mbyte. Most of the data store space is reserved for storage of received and transmitted data, with some areas reserved for use by firmware. However, a portion of the data store may be allocated as code store. This permits higher speed instruction execution, by using fast RAMs, than is possible from Flash memories. The maximum size of this overlay is the full code space address range, 128Kbytes, and is allocated in independent sections of 16KBytes each, on 16Kbyte boundaries, ranging from the highest address of the actual physical memory space and extending down. Mapping code execution to RAM requires the RAM to have code written into it. Typically, this is done by placing code in a non-volatile memory such as a Flash in the code space. At initialization, the code in the non-volatile memory transfers itself to RAM, maps the appropriate blocks of the code space to the RAM, and then branches to begin execution from RAM. This allows low cost, slow Flash devices to hold an entire code image, which can be executed much faster from RAM. If code is not placed in an external non-volatile memory as described here, it must be transferred to the RAM via the Host Interface. 2-16
Slow memories are not dynamically sensed. Following reset, the instruction clock operates with a slower cycle while the Flash is copied to RAM. Once code has been copied from Flash to RAM, execution transfers to RAM and the clock is raised to the normal operating frequency. As mentioned above, it is feasible to operate without a code image in a non-volatile memory. In such a system, the firmware must be downloaded to RAM through the host interface before operation can commence. The external SRAM memory must be organized in a 16-bit width to provide adequate performance to implement the 802.11 protocol at 11Mb/s rates. Systems designed for lower performance applications may be able to use 8-bit wide memory. The minimum external memory is 128Kbytes of SRAM, organized 8 or 16 bits wide. Typical applications, including 802.11 station designs, use 256Kbytes organized 128K x 16. An access point application could make use of the full address space of the device with 4Mbytes organized a 2M x 16. The HFA3842 supports 8 or 16 bit code space, and 8 or 16-bit data space. Code space is typically populated with the lease expensive Flash memory available, usually an 8-bit device. Data space is usually populated with high-speed RAMs configured as a 16-bit space. This mixing of 8/16 bit spaces is fully supported, and may be done in any combination desired for code and data space. The HFA3842 supports direct control of single chip 16-bit wide SRAMs with high/low byte enables, as well as direct
HFA3842
control of a 16-bit space constructed from 8-bit wide SRAMs. The type of memory configuration is specified via the appropriate MD pin, sensed when the HFA3842 is reset. HFA3842 pin MUBE-/MA0/MWEH- functions as Address 0 for 8-bit access, (such as Flash) as MWEH (High Byte Write Enable) when two x8 memories are configured as a single x16 space, and as the upper Byte Enable when a single x16 memory is used. No external logic is required to generate the required signals for both types of memory configurations, even when both exist together; all that is required is for the HFA3842 code to configure the HFA3842 memory controller to generate the proper signals for the particular address space being accessed. For 8-bit spaces, the HFA3842 dynamically configures pin MUBE-/MA0/MWEH- cycle-by-cycle as the address LSB. MWEL-/MWE- is the only write control, and MOE- is the read output enable. For 16-bit spaces constructed from 8-bit memories, the HFA3842 dynamically configures pin MUBE-/MA0/MWEHcycle-by-cycle as the high byte write enable, MWEL- as the low write enable signal, and MOE- as the read output enable. For 16-bit spaces constructed from single-chip x16 memories (such as SRAMs), the HFA3842 dynamically configures pin MUBE_/MA0/MWEH- cycle-by-cycle as the upper byte enable. Pin MLBE- is connected as the low byte enable, MWEL-/MWE- is the write control, and MOE- is the read output enable. These memory implementations require no external logic. The memory spaces may each be constructed from any type of memory desired. The only restriction is that a single memory space must be constructed from the same type of memory; for example, data space may not use both x8 and x16 memories, it must be all x8, or all x16. This restriction does not apply across memory spaces; e.g., code space may use a x8 memory and data space a single x16 memory, or code space two x8 memories and data space a single x8 memory. Contact the factory for additional information in regards to HFA3842 to PRISM II MAC-less Connections. CIS table which is located in external memory. Common memory is not used. The following describes specific features of various pins: HA[9:0] Decoding of the system address space is performed by the HCEx-. During I/O accesses HA[5:0] decode the register. HA[9:6] are ignored when the internal HAMASK register is set to the defaults used by the standard firmware. During attribute memory accesses HA[9:1] are used. HD[15:0] The host interface is primarily designed for word accesses, although all byte access modes are fully supported. See HCE1-, HCE2- for a further description. Note that attribute memory is specified for and operates with even bytes accesses only. HCE1-, HCE2The PC Card cycle type and width are controlled with the CE signals. Word and Byte wide accesses are supported, using the combinations of HCE1-, HCE2-, and HA0 as specified in the PC Card standard. HWE-, HOEHOE- and HWE- are only used to access attribute memory. Common Memory, as specified in the PC Card standard, is not used in the HFA3842. HOE- is the strobe that enables an attribute memory read cycle. HWE- is the corresponding strobe for the attribute memory write cycle. The attribute space contains the Card Information Structure (CIS) as well as the Function Configuration Registers (FCR). HIORD-, HIOWRHIORD- and HIOWR- are the enabling strobes for register access cycles to the HFA3842. These cycles can only be performed once the initialization procedure is complete and the HFA3842 has been put into IO mode. HREGThis signal must be asserted for I/O or attribute cycles. A cycle with HREG- unasserted will be ignored as the HFA3842 does not support common memory. HINPACKThis signal is asserted by the HFA3842 whenever a valid I/O read cycle takes place. A valid cycle is when HCE1-, HCE2-, HREG-, and HIORD- are asserted, once the initialization procedure is complete. HWAITWait states are inserted in accesses using HWAIT-. The host interface synchronizes all PC Card cycles to the internal HFA3842 clock. The following wait states should be expected:
Host Interface
PC Card Physical Interface
The Host interface is compatible to the PC Card 95 Standard (PCMCIA v2.1). The HFA3842 Host Interface pins connect directly to the correspondingly named pins on the PC Card connector with no external components (other than resistors) required. The HFA3842 operates as an I/O card using less than 64 octet locations. Reads and writes to internal registers and buffer memory are performed by I/O accesses. Attribute memory (256 octets) is provided for the
2-17
HFA3842
Direct Read or Write to Hardware Register * 1/2 to 1 MCLK assertion of HWAIT- for internal synchronization. Write to Memory Mapped Register, Buffer Access Path, or Attribute Space (Post-Write) * The data required for the write cycle will be latched and therefore only the synchronizing wait state will occur. * Until the queued cycle has actually written to the memory, any subsequent access by the Host will result in a WAIT. Read to Attribute Space and Memory Mapped Registers * WAIT will assert until the memory arbitration and access have completed. Buffer Access Paths, BAP0 and BAP1 * An internal Pre-Read cycle to memory is initiated by a host Buffer Read cycle, after the internal address pointer has auto-incremented. If the next host cycle is a read to the same buffer, the data will be available without a memory arbitration delay. * A single register holds the pre-read data. Thus, any read access to any other memory-mapped register (or the other buffer access path) will result in the pre-read data becoming invalidated. * If another read cycle has invalidated the pre-read, then a memory arbitration delay will occur on the next buffer access path read cycle. HIREQImmediately after reset, the HIREQ- signal serves as the RDY/BSY (per the PC Card standard). Once the HFA3842 firmware initialization procedure is complete, HIREQ- is configured to operate as the interrupt to the PC Card socket controller. Both Level Mode and Pulse Mode interrupts are supported. By default, Level mode interrupts are used, so the interrupt source must be specifically acknowledged or disabled before the interrupt will be removed. HRESET When reset is removed, the CIS table is initialized and, once complete, HIREQ- is set high (HIREQ- acts as RDY/BSY from reset and is set high to indicate the card is ready for use). The CIS table resides in Flash memory and is copied to RAM during firmware initialization. The host system can then initialize the card by reading the CIS information and writing to the configuration register.
ISA PnP
The HFA3842 can be connected to the ISA bus and operate in a Plug and Play environment with an additional chip such as the Fujitsu MB86703, Texas Instruments TL16PNP200A, or Fairchild Semiconductor NM95MS15. See the Application Note AN9874, "ISA Plug and Play with the HFA3841" for more details.
Register Interface
The logical view of the HFA3842 from the host is a block of 32 word wide registers. These appear in IO space starting at the base address determined by the socket controller. There are three types of registers. HARDWARE REGISTERS (HW) * 1 to 1 correspondence between addresses and registers. * No memory arbitration delay, data transfer directly to/from registers. * AUX base and offset are write-only, to set up access through AUX data port. * Note: All register cycles, including hardware registers, incur a short wait state on the PC Card bus to ensure the host cycle is synchronized with the HFA3842's internal MCLK. MEMORY MAPPED REGISTERS IN DATA RAM (MM) * 1 to 1 correspondence. * Requires memory arbitration, since registers are actually locations in HFA3842 memory. * Attribute memory access is mapped into RAM as Baseaddress + 0x400. * AUX port provides host access to any location in HFA3842 RAM (reserved). BUFFER ACCESS PATH (BAP) * No 1 to 1 correspondence between register address and memory address (due to indirect access through buffer address pointer registers). * Auto increment of pointer registers after each access. * Require memory arbitration since buffers are located in
TABLE 7. MEMORY MAPPED REGISTER I/O OFFSET 00 02 04 06 08 0A Command Param0 Param1 Param2 Status Resp0 NAME TYPE MM MM MM MM MM MM
2-18
HFA3842
TABLE 7. MEMORY MAPPED REGISTER (Continued) I/O OFFSET 0C 0E 10 20 22 24 18 1C 36 1A 1E 38 30 32 34 14 28 2A 2C 3A 3C 3E Resp1 Resp2 InfoFID RxFID AllocFID TxComplFID BAP Select0 BAP Offset0 BAP Data0 BAP Select1 BAP Offset1 BAP Data1 EvStat IntEn EvAck Control SwSupport0 SwSupport1 SwSupport2 AuxBase AuxOffset AuxData NAME TYPE MM MM MM MM MM MM MM MM BAP MM MM BAP HW HW HW MM MM MM MM HW HW (Reserved)
Buffer Access Paths
The HFA3842 has two independent buffer access paths, which permits concurrent read and write transfers. The firmware provides dynamic memory allocation between Transmit and Receive, allowing efficient memory utilization. On-the-fly allocation of (128-byte) memory blocks as needed for reception wastes minimal space when receiving fragments. The HFA3842 hides management of free memory from the driver, and allows fast response and minimum data copying for low latency. The firmware provides direct access to TX and RX buffers based on Frame ID (FID). This facilitates Power Management queuing, and allows dynamic fragmentation and defragmentation by controller. Simple Allocate/Deallocate commands ensure low host CPU overhead for memory management. Hardware buffer chaining provides high performance while reading and writing buffers. Data is transferred between the host driver and the HFA3842 by writing or reading a single register location (The Buffer Access Path, or BAP). Each access increments the address in the buffer memory. Internally, the firmware allocates blocks of memory as needed to provide the requested buffer size. These blocks may not be contiguous, but the firmware builds a linked list of pointers between them. When the host driver is transferring data through a buffer access path and reaches the end of a physical memory block, hardware in the host interface follows the linked list so that the buffer access path points to the beginning of the next memory block. This process is completely transparent to the host driver, which simply writes or reads all buffer data to the same register. If the host driver attempts to access beyond the end of the allocated buffer, subsequent writes are ignored, and reads will be undefined.
2-19
HFA3842
FID
BUFFER DESCRIPTOR ACCESS (FIRMWARE)
BUFFER MEMORY VIRTUAL FRAME BUFFER STATUS
ALLOCATE/ DEALLOCATE REQUEST OFFSET CENTER HOST BUS DATA PORT PRE-READ/ POST-WRITE
BLOCK A OFFSET
HEADER
D DATA
FIGURE 14. BLOCK DIAGRAM OF A BUFFER ACCESS PATH
PHY Interface
The HFA3842 is intended to support the PRISM family of Baseband processors with no additional components. This family currently includes the HFA3860B, HFA3861B, HFA3861 and HFA3863 baseband processors and the other ICs in the PRISM radio chip set. (Other baseband processors may be supported with custom firmware. See your sales representative for more information). The HFA3842 interfaces to the HFA386X baseband processors through two serial interfaces. The Modem Management Interface (MMI) is used to read and write internal registers in the baseband processor and access per-packet PLCP information. The Modem Data Interface (MDI) provides the receive and transmit data paths which transfer the actual MPDU data.
PHY BASEBAND PROCESSOR The PHY baseband processor is programmed by HFA3842 firmware. The PRISM II baseband processor mode works as follows: The Control Port consists of 4 signals: SD (serial data), SCLK (serial clock), R/W (read/write) and CS_BAR (activelow chip select). Control Port signaling for read and write operations is illustrated in Figures 15 and 16 respectively. Detailed timing relationships appear in Figure 17 and timing specifications are contained in Table 8. The BBP always uses the rising edge when clocking data on the Control Port. This means that when the BBP is receiving data it uses the rising edge of clock to sample; when driving data, transitions occur on the rising edge. Address bits 6 through 1 are significant for selecting configuration registers. Address bits 7 and 0 are unused. See the BBP Programming section for register addresses and suggested values. For read operations, the rising edge of R/W must occur after the 7th but prior to the 8th rising edge of SCLK. This ensures that the first data bit is clocked out of the BBP prior to the edge used to clock it into the MAC. For more detailed information on the Control Port and BBP register programming see the HFA386x data sheets.
Serial Control Port (MMI)
The HFA3842 has a serial port that is used to program the baseband processor. There are individual chip selects and shared clock and data lines. The MMI is used to program the registers and functionality of the PHY baseband processor.
2-20
HFA3842
FIRST ADDRESS BIT 7 SCLK 6 5 4 3 2 1 0
FIRST DATABIT OUT 7 6 5 4 3 2 1 0
SD
7 MSB
6
5
4
3
2
1
07 7 6 6 5 MSB
4
3
2
1
0 LSB
ADDRESS IN
DATA OUT
R/W CS
FIGURE 15. PRISM II BASEBAND PROCESSOR CONTROL PORT READ TIMING
7 SCLK
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SD
7 MSB
6
5
4
3
2
1
0
7 MSB
6
5
4 DATA IN
3
2
1
0 LSB
ADDRESS IN
R/W
CS
FIGURE 16. PRISM II BASEBAND PROCESSOR SERIAL CONTROL PORT WRITE TIMING
tSCP tSCW tSCW
SCLK tSCS SDI, R/W, SD, CS tSCD SD (AS OUTPUT) tSCH
R/W SD tSCED tSCED
FIGURE 17. BBP CONTROL PORT SIGNAL TIMING
2-21
HFA3842
TABLE 8. BBP CONTROL PORT AC ELECTRICAL SPECIFICATIONS PARAMETER SCLK Clock Period SCLK Width Hi or Low Setup to SCLK + Edge (SD, SDI, R/W, CS) Hold Time from SCLK + Edge (SD, SDI, R/W, CS) SD Out Delay from SCLK + Edge SD Out Enable/Disable from R/W SYMBOL tSCP tSCW tSCS tSCH tSCD tSCED MIN 90 20 30 0 MAX 30 15 UNITS ns ns ns ns ns ns
The MDI performs the following functions: * Serial to parallel conversion of received data from the baseband, with synchronization between the incoming RX clock to the internal HFA3842 clock. * Generating CRCs (HEC and FCS) from the received data stream to verify correct reception. * Decrypt the received data when WEP is enabled. * Parallel to serial conversion of transmit data, with the serial timing synchronized with the TX clock. * Insertion of the CRCs (HEC and FCS) at the appropriate point during transmission. * Encrypt the transmitted data when WEP is enabled. The receive data path uses RX_RDY, RXC, RXD. The transmit data path uses TX_RDY, TXC, TXD and the CCA input to determine (under the IEEE802.11 protocol) whether to transmit. In transmit mode, the HFA386X is used in the mode where it generates the PLCP header internally and only the MPDU is passed from HFA3842. In receive, the HFA386X is used in the mode where it passes the PLCP header and the MPDU to the HFA3842.
SYNTHESIZER For the PRISM(R) II, the synthesizer is programmed by firmware using different pins than the MMI. The HFA3842 will exchange data with the baseband during transmit and receive operations over the MMI interface. If the MMI interface was connected to the front end chips, the transitions on SCLK and SD could couple noise into them. The synthesizer serial bus consists of SYNTHDATA, SYNTHCLK, LE_IF and LE_RF. SYNTHDATA is on pin PK2, SYNTHCLK is on PK1, LE_IF is the enable for the HFA3783 Quad IF chip, and LE_RF is the enable for the HFA3683 synthesizer. Data is provided on SYNTHDATA and clock on SYNTHCLK. The data is updated the falling edge of SYNTHCLK and expected to be latched into the synthesizer on the rising edge. The enable signal LE_RF is asserted while data is clocked out.
LE_RF
BBP Packet Reception
There are 4 signals associated with the BBP Receive Port: RX_PE (Receive Enable), MDRDY (Receive Ready), RXD (Receive Data), and RXCLK (Receive Clock). These connect to the HFA3842 on pins PL1, PK5, RXD, and RXC, respectively. The receive demodulator in the BBP is activated via RX_PE. When RX_PE goes active the demodulator scrutinizes I and Q for packet activity. When a packet arrives at a valid signal level the demodulator acquires and tracks the incoming signal. It then sifts through the demodulator data for the Start Frame Delimiter (SFD). Normally, MDRDY is programmed to go active after SFD is detected. This signals the HFA3842, allowing it to pick off the needed header fields from the realtime demodulated bitstream rather than having to read these fields through the BBP Control Port. Assuming all is well with the header, the BBP decodes the signal field in the header and switches to the appropriate data rate. If the signal field is not recognized, or the CRC16 is in error, then MDRDY will go inactive shortly after CRC16 and the demodulator will return to acquisition mode looking for another packet. If all is well with the header, and after the demodulator has switched to the appropriate data rate, then the demodulator will continue to provide data to the HFA3842 indefinitely. Receive Port exchange details are depicted in Figure 19. Detailed timing is related in Figure 20 and Table 9. For more detailed information concerning BBP packet reception see the HFA386x data sheets.
SYNTHCLK
SYNTHDATA
D23
D22 D21 D20
D1
D0
FIGURE 18. SYNTHESIZER DATA FORMAT
PHY Data Interface (MDI)
The HFA3842 has a dedicated serial port to provide the data interface to the baseband processor. This is referred to as the Modem Data Interface (MDI). The MDI operates on the data being transferred to and from the baseband on a word by word basis. There are no FIFOs needed, since the firmware is able to control the protocol in real time.
2-22
HFA3842
RXC
RX_PE
HEADER FIELDS DATA
MDRDY
PROCESSING PREAMBLE/HEADER
LSB RXD
DATA PACKET
MSB
FIGURE 19. BBP RECEIVE PORT TIMING
tRLP RX_PE
tRD3 tREH IIN , QIN tRD2
MDRDY
tRCP
RXC tRCD
RXD
tCCA tRDS tRDI tRDD
tRCD
CCA, RSSI
FIGURE 20. BBP RECEIVE PORT SIGNAL TIMING NOTE: RXD, MDRDY is output two MCLK after RXC rising to provide hold time. RSSI output on TEST (5:0).
TABLE 9. BBP RECEIVE PORT AC ELECTRICAL SPECIFICATIONS PARAMETER RX_PE Inactive Width RXC Period (11MBps Mode) RXC Width Hi or Low (11MBps Mode) RXC to RXD MD_RDY to 1st RXC RXD to 1st RXC Setup RXD to RXC RXC to RX_PE Inactive (1MBps) RXC to RX_PE Inactive (2MBps) RXC to RX_PE Inactive (5.5MBps) RXC to RX_PE Inactive (11MBps) SYMBOL tRLP tRCP tRCD tRDD tRD1 tRD! tRDS tREH tREH tREH tREH MIN 70 77 31 20 940 940 31 0 0 0 0 MAX 60 925 380 140 50 UNITS ns (Note 16) ns ns ns ns (Note 17) ns ns ns (Note 18) ns (Note 18) ns (Note 18) ns (Note 18)
2-23
HFA3842
TABLE 9. BBP RECEIVE PORT AC ELECTRICAL SPECIFICATIONS (Continued) PARAMETER RX_PE inactive to MD_RDY Inactive Last Chip of SFD in to MD_RDY Active RX Delay RX_PE to CCA Valid RX_PE to RSSI Valid NOTES: 16. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition. 17. MD_RDY programmed to go active after SFD detect (measured from IIN, QIN). 18. RX_PE active to inactive delay to prevent next RXC. 19. Assumes RX_PE inactive after last RXC. 20. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at IIN, QIN to MD_RDY active. 21. CCA and RSSI are measured once during the first 10s interval following RX_PE going active. RX_PE must be pulsed to initiate a new measurement. RSSI may be read via serial port or from Test Bus. tCCA tCCA SYMBOL tRD2 tRD3 MIN 5 2.77 2.77 MAX 30 2.86 2.86 10 10 UNITS ns (Note 19) s (Note 17) s (Note 20) s (Note 21) s (Note 21)
BBP Packet Transmission
There are 4 signals associated with the BBP Transmit Port: TX_PE (Transmit Enable), TXRDY (Transmit Ready), TXD (Transmit Data), and TXCLK (Transmit Clock). These connect to the HFA3842 on PL0, PL7, TXD, and TXC, respectively. State machines within the BBP control packet transmission and reception. In the case of a transmission, the MAC signals the BBP with the signal TX_PE. The BBP forms the preamble and header and then signals the MAC to begin transferring data with the signal TXRDY. This sequence is illustrated in Figure 21 with detailed signal timing shown in Figure 22 and specified delays contained in Table 10. Note that if the MAC deactivates TX_PE too early it may cut off modulation of the final symbol. For this reason, when TX_PE is de-asserted the BBP will hold TXRDY active until the last symbol containing data is modulated. This is important for power sequencing and is discussed in more detail in that section. For more detailed information concerning BBP packet transmission see the HFA3861 data sheet.
TABLE 10. BBP TRANSMIT PORT AC ELECTRICAL SPECIFICATIONS PARAMETER TX_PE to IOUT/QOUT (1st Valid Chip) TX_PE Inactive Width TXC Width Hi or Low TXRDY Active to 1st TX_CLK Hi Setup TXD to TXC Hi Hold TXD to TXC Hi SYMBOL tD1 tTLP tTCD tRC tTDS tTDH MIN 2.18 2.22 40 260 30 0 MAX 2.3 UNITS s (Note 22) s (Note 23) ns ns ns ns
TABLE 10. BBP TRANSMIT PORT AC ELECTRICAL SPECIFICATIONS PARAMETER TXC to TX_PE Inactive (1MBps) TXC to TX_PE Inactive (2MBps) TXC to TX_PE Inactive (5.5MBps) TXC to TX_PE Inactive (11MBps) TXRDY Inactive To Last Chip of MPDU Out TXD Modulation Extension NOTES: 22. IOUT/QOUT are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits. 23. TX_PE must be inactive before going active to generate a new packet. 24. IOUT/QOUT are modulated after last chip of valid data to provide ramp down time for RF/IF circuits. 25. Delay from TXC to inactive edge of TXPE to prevent next TXC. Because TXPE asynchronously stops TXC, TXPE going inactive within 40ns of TXC will cause TXC minimum hi time to be less than 40ns. SYMBOL tPEH tPEH tPEH tPEH tRI MIN 0 0 0 0 -20 MAX 965 420 160 65 20 UNITS ns (Note 25) ns (Note 25) ns (Note 25) ns (Note 25) ns
tME
2
-
s (Note 24)
2-24
HFA3842
TXC
TX_PE
FIRST DATA BIT SAMPLED
LAST DATA BIT SAMPLED
TXD
LSB
DATA PACKET
MSB DEASSERTED WHEN LAST CHIP OF MPDU CLEARS MOD PATH OF 3861
TXRDY
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXC. FIGURE 21. BBP TRANSMIT PORT TIMING
tTLP TX_PE tDI IOUT, QOUT tRI TXRDY tRC TXC TXD tTDH tTDS tTCD t TCD tPEH tME
FIGURE 22. BBP TRANSMIT PORT SIGNAL TIMING
USB Port
The USB interface implemented in the HFA3842 complies with the Universal Serial Bus Specification Revision 1.1. dated September 23, 1998, which is available from the USB Implementers' Forum at http://www.usb.org/. The USB host port interface uses Microsoft's Remote NDIS protocol to communicate with the network software on the host computer. The USB supports 4 endpoints. * One Communications Class control endpoint for interface management; * One Communications Class interrupt endpoint for signalling interrupts to the host; and * Two Bulk endpoints for transfer of encapsulated NDIS functions to and from the host. The USB along with USB support firmware provides an alternate host interface for attaching an 802.11{b} WLAN adapter to a host computer. This interface does not provide 2-25 "wireless USB" where USB packets are sent on the wireless medium due to timing constraints in the USB protocol. USB+ and USB- are the differential pair signals provided for the user. These signals are capable of directly driving a USB cable. USB_DETECT is a 5V tolerant input to the HFA3842 device. It is used to signal the MAC processor that a USB cable is attached to the unit. Complete details on the USB firmware for controlling this port can be obtained by contacting the factory directly.
HFA3842 Power Sequencing
The HFA3842 provides a number of firmware controlled port pins that are used for controlling the power sequencing and other functions in the front end components of the PHY. Packet transmission requires precise control of the radio. Ideally, energy at the antenna ceases after the last symbol of information has been transmitted. Additionally, the transmit/receive switch must be controlled properly to protect the receiver. It's also important to apply appropriate modulation to the PA while it's active. Signaling sequences for the beginning and end of normal transmissions are illustrated in Figure 23. Table 11 lists applicable delays. A transmission begins with PE2 as shown in Figure 23. Next, the transmit/receive switch is configured for transmission via the differential pair TR_SW and TR_SW_BAR. This is followed by TX_PE which activates the transmit state machine in the BBP. Lastly, PA_PE activates the PA. Delays for these signals related to the initiation of transmission are referenced to PE2. Immediately after the final data bit has been clocked out of the HFA3842, TX_PE is de-asserted. The HFA3842 then waits for TXRDY to go inactive, signaling that the BBP has modulated the final information-rich symbol. It then immediately de-asserts PA_PE followed by placing the transmit/receive switch in the receive position and ending with PE2 going high. Delays for these signals related to the termination of transmission are referenced to the rising edge of PE2.
PE1
PE2
TR_SW TR_SW_BAR
tD1
tD5
TX_PE tD2
TX_RDY
PA_PE tD3 tD4
FIGURE 23. TRANSMIT CONTROL SIGNAL SEQUENCING
TABLE 11. TRANSMIT CONTROL TIMING SPECIFICATIONS PARAMETER PE2 to TR Switch PE2 to BBP TX_PE PE2 to PA_PE PA_PE to PE2 TR Switch to PE2 SYMBOL tD1 tD2 tD3 tD4 tD5 DELAY 2 TBD 3 3 2 TOLERANCE UNITS 0.1 0.1 0.1 0.1 0.1 s s s s s
2-26
HFA3842
PE1 and PE2 encoding details are found in Table 12. Note that during normal receive and transmit operation that PE1 is static and PE2 toggles for receive and transmit states
.
TABLE 12. POWER ENABLE STATES PE1 Power Down State Receive State Transmit State PLL Active State PLL Disable State NOTE: 26. PLL_PE is controlled via the serial interface, and can be used to disable the internal synthesizer, the actual synthesizer control is an AND function of PLL_PE, and a result of the OR function of PE1 and PE2. PE1 and PE2 will directly control the power enable functionality of the LO buffer(s)/phase shifter. 0 1 1 0 X PE2 0 1 0 1 X PLL_PE 1 1 1 1 0
which is the same function, when an external clock is provided to the MAC controller (as is recommended when using the HFA3842 with PRISM radios). The low-frequency crystal attaches between pin 39 (which is a 3.3V power input for the high-frequency oscillator on the HFA3841) and pin 41 (which is XTALO on the HFA3841, hence, unconnected if the on-chip oscillator is not being used). Refer to Figure 24 for further details. If a 32.768KHz crystal is connected, the resulting LF clock is supplied to an interval timer to permit measuring sleep intervals as well as providing a programmable wake-up time. In addition, the CHOICE-W clock generator can operate either from CLKIN or (very slowly) from the LF clock. Glitchfree switching between these two clock sources, under firmware control, is provided by two, non-architectural Strobe functions ("FAST" and "SLOW"). In addition, during hardware reset, the clock generator source is set to the LF clock if no edges are detected on CLKIN for two cycles of the LF clock (roughly 61 microseconds). This allows proper initialization with omission of either clock source, since without the LF crystal attached there will not be cycles of the LF clock to activate the detection circuit. The ability to initialize the HFA3842 using the LF oscillator to generate MCLK allows the high-frequency (PHY) oscillator to be powered down during sleep state, which is not possible with the HFA3841. If this is done, firmware can turn on power to the PHY oscillator upon wakeup, and use the interval timer to measure the startup and stabilization period before switching to use CLKIN.
Master Clock
Prescaler
The HFA3842 contains a clock prescaler to provide flexibility in the choice of clock input frequencies. For 11Mb/s operation, the internal master clock, MCLK, must be between 11MHz and 16MHz. The clock generator itself requires an input from the prescaler that is twice the desired MCLK frequency. Thus the lowest oscillator frequency that can be used for an 11MHz MCLK is 22MHz. The prescaler can divide by integers and 1/2 steps (IE 1, 1.5, 2, 2.5). Another way to look at it is that the divisor ratio between the external clock source and the internal MCLK may be integers between 2 and 14. Typically, the 44MHz baseband clock is used as the input, and the prescaler is set to divide by 2. Another useful configuration is to set the prescaler to divide by 1.5 (resulting in 44MHz /3) for an MCLK of 14.67MHz. Contact the factory for further details on setting the clock prescaler register in the HFA3842.
Clock Generator
The HFA3842 can operate with MCLK frequencies up to at least 25MHz and CLKIN frequencies of at least 50MHz. The MCLK prescaler generates MCLK (and QCLK) from the external clock provided at the CLKIN input, or from the output of the LF oscillator. The MCLK prescaler divides the selected input clock by any integer value between 2 and 16, inclusive. * When using a 44MHz CLKIN, as is typical for 802.11 or 802.11b controllers with a PC Card Host Interface, common divisors are 3 (14.67MHz), 4 (11MHz), or 5 (8.8MHz) * When using a 48MHz CLKIN, as is typical for 802.11 or 802.11b controllers with a USB host interface, common divisors are 3 (16MHz), 4 (12MHz), or 6 (8MHz) * It is anticipated that a controller for the 802.11a, mandatory data rates will need to operate at an MCLK frequency of a least 24MHz, hence a CLKIN frequency of at least 48MHz. The MCLK prescaler is set to divide by 16 at hardware reset to allow initialization firmware to be executed from slow memory devices at any CLKIN frequency. The MCLK prescaler generates glitch free output when the divisor is changed. This allows firmware to change the MCLK
Low-Frequency Crystal
The HFA3842 has on on-chip high-frequency oscillator that can be used to generate the internal master clock (MCLK). However, this on-chip high-frequency oscillator is almost never used because the MAC controller can accept the same clock signal as the PHY baseband processor (typically 44MHz), thereby avoiding the need for a separate, MACspecific oscillator in close proximity to the PHY RF circuitry. Therefore, on the HFA3842 the high-frequency oscillator is replaced by a low-frequency oscillator. This low-frequency oscillator is intended for use with a 32.768KHz, tuning-fork type watch crystal to permit accurate timekeeping with very low power consumption during sleep state. For the HFA3842 to achieve footprint compatibility with the HFA3841, pin 40 (OSCIN on the HFA3841) becomes CLKIN, 2-27
HFA3842
frequency during operation, which is especially useful to selectively reduce operating speed, thereby conserving power, when full speed processing is not required.
LFXTALI XTALI 39 LFXTALO 4700pF X1 41 10M C2 22pF C1
References
For Intersil documents available on the internet, see web site http://www.intersil.com/ Intersil AnswerFAX (321) 724-7800. [1] IEEE Std 802.11-1999 Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specification. [2] HFA3860B Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4594. [3] HFA3861 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4699. [4] HFA3783 Data Sheet, Quad IF, Intersil Corporation, AnswerFAX Doc. No. 4633. [5] HFA3683 Data Sheet, Direct Sequence Spread Spectrum Baseband Processor, Intersil Corporation, AnswerFAX Doc. No. 4634. [6] PC Card Standard 1996, PCMCIA/JEIDA. [7] AN9874 Application Note, Intersil Corporation, "ISA Plug and Play with the HFA3841". [8] AN9844 Application Note, Intersil Corporation, "HFA3842 to PRISM II MAC-less Connections", AnswerFAX Doc. No. 99844. [9] AN9893 Application Note, Intersil Corporation, AnswerFAX Doc. No. 99893 "Using the HFA3842 WLAN MAC Evaluation Board".
FIGURE 24. 32.768kHz CRYSTAL
Power On Reset Configuration
Power On Reset is issued to the HFA3842 with the HRESET pin or via the soft reset bit, SRESET, in the Configuration Option Register (COR, bit 7). HRESET originates from the HOST system which applies HRESET for at least 0.01ms after VCC has reached 90% of its end value (see PC-Card standard, Vol. 2, Ch. 4.12.1). The MD[15:8] pin values are sampled on the falling edge of HRESET or SRESET. These pins have internal 50K pulldown resistors. External pull-up resistors (typically 10k) are used for bits that should be read as high at reset. The table below summarizes the effect per pin.
TABLE 13. POR PINS AND FUNCTIONALITY PIN MD[8] MD[9] MD[10] MD[11] MD[12] MD[15:13] LATCH OUTPUT Reserved Nvdis MEM16 IDLE Reserved MD15/14/13 FW Purposes Disable Mapping of CS to NV (Flash) External Memory (RAM and Flash) is 16 bits Wide See Below FUNCTIONALITY
MD[11], IDLE, has no equivalent functionality in any control register. When asserted at reset, it will inhibit firmware execution. This is used to allow the initial download of firmware in "Genesis Mode". The latch is cleared when the Software Reset, SRESET, COR(7) is active.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 2-28

▲Up To Search▲

Price & Availability of HFA3842

	To Download HFA3842 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .